The present invention relates in general to recovering a clock signal for a digital data transmission, and, more specifically, to recovering a clock signal without requiring a data receiver to adopt a sampling frequency that is an integer multiple of the data bit rate.
When generating digital information in the form of binary signals, each binary bit is assigned to a respective time slot. The time slots are typically of equal duration as determined by a clock signal having a frequency corresponding to the desired bit rate of the binary signal. To assist in the transmission of the digital signal (e.g., in wireless radio communication), a modulation scheme may be used to represent a binary one or zero value. When such a signal is received, the detection or demodulation of the original binary signal depends on timing information being available to identify the correct time slots. It is usually not practical to transmit the original clock signal with the binary data signal. Consequently, it is usually desirable to recover the clock timing from the transmitted data signal itself.
The Radio Data System (RDS) in Europe and the Radio Broadcast Data System (RBDS) in North America are examples of systems employing wireless broadcasting of digital data. In these systems, a digital data stream supplementing an analog radio (e.g., FM) broadcast is broadcast on a subcarrier using binary modulated signals. By properly demodulating the encoded data, the digital data stream is able to provide the receiver with various enhanced features, such as textual display of program or format type identification, displaying broadcaster name identification, displaying song information (e.g., song title and artist), and providing alternate frequencies for automatic retuning of a radio receiver to another transmitter in a common network when the signal from the current transmitter becomes weak, for example.
The RDS/RBDS data is added to a multiplexed FM broadcast signal using double-sideband, suppressed carrier modulation at a frequency of 57 kHz. The digital data is bi-phase encoded at a data rate of 1,187.5 bits per second. Each binary bit (i.e., either a one or a zero) is represented by a symbol wherein the transitional direction of the time varying signal at the midpoint of a bit time slot signifies the bit value. In order to decode the proper bit values, a proper clock timing signal must be recovered so that the relative phase of each bit symbol can be distinguished.
In prior art RDS/RBDS receivers, the sampling frequency at which the bi-phase encoded data is sampled has been chosen as an integer multiple of the bit rate (i.e., an even amount of integer samples occur during a time slot of the digital data). As a result, it becomes straightforward to generate a clock signal matching the frequency of the bit rate (e.g., by counting at the sample rate to create an alternating clock signal). The clock signal must also have its phase aligned with the original clock signal. The phase alignment can be accomplished by referencing to the data itself.
Requiring the sampling frequency to be a multiple of the data bit rate may be an undesirable constraint on the design of a particular receiver. In addition, prior art clock recovery implementations have been customized to each particular receiver and have not been portable to other receiver designs. With each new model of a receiver, a new, unique clock recovery apparatus must be designed in accordance with other details of the receiver design (e.g., sampling frequency and data bit rate). The effort to create a custom design results in increased cost and development time.